32
9152BINDCO02/10
ATA8743
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-
nal data SRAM in the ATtiny24/44/84 are all accessible through all these addressing modes.
The Register File is described in General Purpose Register File on page 26.
Figure 13-2. Data Memory Map
13.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU
cycles as described in Figure 13-3 on
page 32.
Figure 13-3. On-chip Data SRAM Access Cycles
32 Registers
64 I/O Registers
Internal SRAM
(128/256/512 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
x DF x 1 F x 2 F
0x0060
Data Memory
clk
WR
RD
Data
Data
ddress
Address valid
T1
T2
T3
Compute Address
CPU
Memory Access Instruction
Next Instruction
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